In modern electronic circuits, such as, for example, input/output (IO) buffers, it is desirable to control the output impedance of the IO buffers for a variety of reasons, including, but not limited to, transmission line matching, minimizing switching noise (di/dt), optimizing signal swing, etc. Various IO standards, such as, for example, stub series terminated logic (SSTL), high-speed transceiver logic (HSTL), etc., specify the output impedance and/or output current of a receiver at specific values of output voltage (e.g., Vol or Voh) in order to ensure that there is sufficient margin for the receiver to function properly. While most IO standards specify an upper limit for output impedance (or a lower limit for output current), switching noise and/or transmission line matching considerations force an even tighter specification on the range of values the output impedance can take.
It has been observed in recent technologies that circuits (e.g., output buffers, drivers, etc.) using passive elements, such as, for example, polysilicon resistors, in series with active devices display tighter variation of output impedance across variations in process, supply voltage and/or temperature (PVT) conditions to which the circuits may be subjected. However, such designs occupy significant silicon area, especially at low values of target output impedance due, at least in part, to electromigration and/or heat dissipation considerations. Such conventional designs are therefore undesirable.
Accordingly, there exists a need for an improved output impedance compensation circuit that does not suffer from one or more of the problems exhibited by conventional output impedance compensation circuitry.